Lecture 1. Introduction and Basics – Carnegie Mellon – Computer Architecture 2015 – Onur Mutlu


Lecture 1. Introduction and Basics
Lecturer: Prof. Onur Mutlu (
Date: Jan 12th, 2015

Lecture 1 slides (pdf):
Lecture 1 slides (ppt):

Course webpage:
Module materials:

Source: https://cyrrion.com
Read more all post Computer Technology : https://cyrrion.com/computer/
  1. Mohamad Rifat Ahmed says

    I actually thought about multi-channel memory at the beginning.

  2. Mohamad Rifat Ahmed says

    Sir is very tricky and smart

  3. Mohamad Rifat Ahmed says

    so even if the operating system schedules the two processes to two cores, which is fair because each process gets its own, but bottleneck is the memory access policy.

  4. Sniper Hawk Gaming says

    33:15 What do you do?Stack Overflow.

  5. Aziz Nighter says

    If he’s gay he can get me right over!!

  6. AHMET EMRE says

    Hocam türk olduğunuzu öğrendiğimde gözümden yaş geliyordu. çok teşekkür ederim böyle bir seri yayınladığınız için

  7. CD says

    Excellent content

  8. Oleksandr Kozmei says

    thanks to all of you, who are related to creating such an amazing educational material

  9. سالم علي سالم says

    Thank you Sir. I want to ask,are there any specific courses I should comprehend to get fully understanding to this course?

  10. Kevin Riley says

    This is a great video, thank you so much! I found the DoS in DRAM caused by multicore processing to be very insightful. The paper he suggested reading (Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems) is freely available and is on the US Microsoft website https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/tr-2007-15.pdf

  11. Eddie Eda says

    This is where EE ends up if you're high on a Thursday night at 1:06am in the morning.

  12. Adhitha Dias says

    Is this an undergrad class? Can't believe only 50 students have taken it!!

  13. Rakesh Kumar says

    camera man be like: No I will only show his face to the viewers not the slides.

  14. Rakesh Kumar says

    Just started watching. I am excited AF.

  15. Tardis Blue says

    onur mutlu muuuu.Türk hocamız.

  16. Charles Peprah says

    This is awesome

  17. CHEN HE says

    thank you, learning form CMU at home

  18. Mahmoud Abd Al-Ghany says

    A very good course, yet the cameraman is not as great

  19. Maruthu pandian says

    worst camera man, not focusing on slides ,,awesome teacher.

  20. Abhai Kollara says

    Great content ! I wish subtitles were available, so I could really speed up the videos

  21. Abhisar Mohapatra says

    Memory Hog Problem (Solution, my thoughts): Considering the bottleneck is memory controller and I see the primary reason is the fetch logic is predefined and hard to control as a static parameter. What if we abstract the functions of the memory controller and leave them as API's to be implemented on the system software layer. What I mean is suppose we if we have an interface to implement scheduling logic, we can actually implement the memory access logic on the device driver of the controller and have the device point to this logic. This makes it more generic.

  22. Xylan says

    the real game changers watch online Lectures.

  23. Anton Wishwa says

    thank you sir.

  24. wai mun keong says

    thank you.!

  25. BŹ么 ALPHA says

    Subscribed , Loked , dude i am not gay but now i can kiss your ass

  26. Ptmp727 says

    Good video, your seem great, unfortunately the intro is way too long, its almost 30 minutes before I get any relevant information, in the middle, there are too many bits of complicated things combined with irrelevant examples, I had to give up after 27 minutes, because I have no clue when you will actually start talking about the basics of computer architecture, which is the title of the video.

  27. 刘凯强 says

    Could you open the cc ? My listening is too bad.

  28. Connor Nusser says

    Question isn't their a problem with selecting rows and columns with a Mux, as if you were to activate multiple rows when activating a column you activate all values that have a row activated?

  29. HARSHA says

    Hi, is all other professors are this good!?

  30. Johnithinuioian says

    It's an absolute and total crime to give free college lessons on Youtube.DO IT MORE OFTEN 😀

  31. John Hilbert says

    Is this guy swiss?

  32. Sangram Rout says

    This is fucking awosome ….thanks a lot mit

  33. pn4k says


  34. blue bird says

    slide notes : http://www.archive.ece.cmu.edu/~ece447/s15/doku.php?id=schedule

  35. Hentai Eyes says

    Finally something that's not basic elementary Shit

  36. pn4k says

    Why here is'nt subtitles?

  37. Harshitha Yendapally says

    Great Tutorials. Thank You

  38. Silent Bob says

    why are there no subtitles here?

  39. Arebetronics says

    Wow! You are awesome, thank you very much for this material!

  40. b1nch3f says

    At 1:34:25, how about throttling the DRAM access. It'll definitely reduce the hammerings and shall not meet the access rates for erroring out adjacent memory rows.

  41. b1nch3f says

    Great explanation, Prof. i'm through 54m into this video, i think using separate row-buffers for each core would solve this issue. Like we do with servers, having multiple cache servers, replica of main servers for data access. Like wise, instead of mutli-cores with one DRAM and single row-buffer, keep the multi-cores with one DRAM but same number of row-buffers as cores. The OS scheduler will do the rest.

  42. Raghu Talluri says

    Is anyone doing the labs? Is there any reading I need to do for doing labs?

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